An MLIR-based Compiling Flow for Heterogeneous Architecture
Original PyLog is a Python-based compiling flow linking high-level Python algorithm development to FPGA hardware designs, compiling Python to HLS C++ code via a Python-implemented IR. This work extends these functionalities to heterogeneous hardware accelerators by transitioning to MLIR (Multi-Level Intermediate Representation). Leveraging MLIR for back-end optimization meets the diverse needs of different hardware platforms. The approach features an exclusive dialect for high-level representation, which can be lowered to various MLIR dialects and ultimately to LLVM IR supported by HPE’s Cray Compiler Environment (CCE). For CPUs and GPUs, it generates machine code using CCE; for FPGAs, it uses ScaleHLS to generate HLS C++ code, continuing development with Xilinx tools. Future updates can easily integrate QIR (LLVM-based IR for quantum programming) to support Quantum Computing.
